Senior Principal Design Verification Engineer

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related
• 12+ years of experience in mixed-signal or analog circuit verification
• Deep understanding of all aspects of mixed-signal verification environment architecture and implementation
• Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration
• Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium)
• Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations
• Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL
• Experience with automotive PMIC or power management IC design and verification
• Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages
• Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification
• Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation
• Excellent problem-solving and debugging skills with strong analytical mindset
• Leadership and mentoring experienc