Senior Mixed Signal DV Engineer

About the Job

Strategic and Technical Leadership

• Collaborate with Process, Packaging, EDA, and other stakeholders to drive the technology roadmap.
• Define verification best practices, represent technical leadership with key customers, and participate in design review and sign-off.
• Partner with Architecture, Design, and Firmware teams for successful product execution.

Verification Strategy and Architecture

• Create detailed verification test plans, test cases, checkers, and coverage metrics with System, Application, and Design teams.
• Lead ground-up UVM verification environments with agents, drivers, monitors, and scoreboards.
• Build and enhance mixed-signal testbenches using schematics, behavioral models, and RTL.

Modeling, Simulation, and Support

• Create analog behavioral models using Verilog-A, Verilog-AMS, Wreal (RNM), or EENet.
• Implement analog checkers and verify I2C, ASI, SPI, and UART protocols.
• Execute RTL and gate-level simulations, manage regressions, and close functional and code coverage through tape-out.
• Resolve complex design and testbench issues and support ATE pattern generation and silicon characterization.

Minimum Requirements

• Bachelor's or master's degree in electrical engineering.
• Minimum 12 years of experience.
• Strong expertise in SystemVerilog and UVM methodologies.
• Proficiency in analog behavioral modeling with Verilog-AMS, Verilog-A, or Wreal (RNM).
• Direct mixed-signal verification experience combining schematics, behavioral models, and RTL.
• Proficiency with Cadence tools including Xcelium, vManager, JasperGold, Virtuoso, AMS Designer, or equivalent environments.
• Hands-on formal verification, connectivity checks, UNR analysis, CDC/RDC assertions, and UPF-based low-power verification experience.

Preferred Skills

• Automation and data-analysis scripting with Python, Perl, or Shell.
• Advanced verification methodology development and EDA vendor collaboration.
• AI/ML-driven verification methodology experience or interest.
• Experience with signal processing, PMICs, high-speed communication interfaces, I2C, SPI, UART, or ASI.
• Experience in silicon debug and collaboration with silicon validation teams.