greenhouse
Senior Engineer Design Verification - Rx
GreenWave RadiosTM
Bengaluru, IND
Senior
Onsite
Discovered 1 weeks ago
perlpython
Role Overview
InnoPhase Inc., DBA GreenWaveTM Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products.
This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!
Key Skills for This Role
perlpython
Full Job Posting
Key Responsibilities:
- You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. • Work on high speed SERDES interface verification such as PCIE but not limited to. • Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. • Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. • Develop and execute verification plans based on design specifications and collaboration with architects and designers. • Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. • Actively working COCOTB based simulation • Usage of Claude to Develop/close the existing task. • Involvement in Analog based simulations to validate the RFA interface • Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. • Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. • Work with FW team to convert DV sequence to FW drivers • Support emulation, FPGA, prototyping efforts. • Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
- Job Requirements:
- Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS. • 5 or more years of experience in ORAN protocol design verification using reference models. • Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. • Experiences in Cadence vManager for DV metrics extraction and regression • Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). • Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. • Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. • Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based • Experiences in GIT, JIRA, MS office suites
- You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model.
- Work on high speed SERDES interface verification such as PCIE but not limited to.
- Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.
- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
- Develop and execute verification plans based on design specifications and collaboration with architects and designers.
- Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
- Actively working COCOTB based simulation
- Usage of Claude to Develop/close the existing task.
- Involvement in Analog based simulations to validate the RFA interface
- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
- Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
- Work with FW team to convert DV sequence to FW drivers
- Support emulation, FPGA, prototyping efforts.
- Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
Benefits:
- Competitive salary and stock options. • Learning and development opportunities. • Employer paid health Insurance. • Earned, Casual, Sick & parental leaves.
Qualifications
- Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
- 5 or more years of experience in ORAN protocol design verification using reference models.
- Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks.
- Experiences in Cadence vManager for DV metrics extraction and regression
- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch.
- Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
- Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based
- Experiences in GIT, JIRA, MS office suites
About GreenWave RadiosTM
Semiconductors150 employeesFounded 2012
Designing energy-efficient semiconductor solutions for 5G cellular networks.
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