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Senior Director, AI NPD Platforms & Engineering Intelligence

onsemi
San Jose, USA
Full-time
Director · 15+ years experience
Onsite
Discovered 1 months ago

Full Job Posting

Qualifications

  • Required Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
  • 15+ years of semiconductor industry experience.
  • 10+ years of leadership experience in product development, EDA, design methodology, CAD, semiconductor software, or AI-enabled engineering environments.
  • Deep understanding of semiconductor development workflows including:
  • Analog design
  • Digital design
  • Verification
  • Physical design
  • Design automation
  • Semiconductor manufacturing flows
  • Experience leading complex cross-functional engineering organizations.
  • Proven ability to influence executive leadership and drive organizational transformation.
  • Preferred Qualifications
  • Advanced degree (MS or PhD) in Electrical Engineering, AI, Machine Learning, Computer Science, or related field.
  • Experience developing AI-enabled EDA tools, semiconductor design automation platforms, or Agentic AI systems.
  • Hands-on experience with:
  • LLMs
  • Retrieval-Augmented Generation (RAG)
  • Multi-Agent Architectures
  • Model Context Protocol (MCP)
  • Workflow Orchestration Platforms
  • Reinforcement Learning
  • AI Copilots
  • Knowledge Graphs
  • Background in organizational AI transformation programs.
  • onsemi is excited to share the base salary range for this position is $216,775.00 to $390,195.00 Range exclusive of fringe benefits or potential bonuses. The final pay rate for the successful candidate will depend on geographic location, skills, education, experience, and/or consideration of internal equity of our current team members. We also offer a competitive benefits package. https://www.onsemi.com/site/pdf/Benefits-Summary-USA.pdf
  • Deep understanding of semiconductor development workflows including: Analog design Digital design Verification Physical design Design automation Semiconductor manufacturing flows
  • Hands-on experience with: LLMs Retrieval-Augmented Generation (RAG) Multi-Agent Architectures Model Context Protocol (MCP) Workflow Orchestration Platforms Reinforcement Learning AI Copilots Knowledge Graphs

Responsibilities

  • Key Responsibilities
  • Define Enterprise AI NPD Vision
  • Develop and execute the long term strategy for Agentic AI-enabled semiconductor product development.
  • Create the roadmap for AI deployment across product planning, architecture, design, verification, physical implementation, characterization, test, reliability, applications, and documentation.
  • Define the maturity model for AI-assisted, AI-enabled, and AI-native development methodologies.
  • Establish objectives, success metrics, and business outcomes tied to engineering productivity and NPD execution.
  • Build the Agentic Design Platform
  • Lead creation of an enterprise Agentic AI framework supporting:
  • Analog design agents
  • Digital design agents
  • Verification agents
  • Layout agents
  • Test engineering agents
  • Applications engineering agents
  • Documentation and requirements agents
  • Program management agents
  • Define standards for agent architecture, interoperability, orchestration, security, and lifecycle management.
  • Partner with engineering, CAD, IT, and infrastructure teams to deploy scalable AI design environments.
  • Govern AI Agents as Strategic IP
  • Establish companywide governance for AI agents and engineering knowledge assets.
  • Develop processes for agent qualification, validation, release, version control, maintenance, retirement, and reuse.
  • Create an "Agent Library" and corporate repository of approved agents, prompts, workflows, and design knowledge.
  • Define review and approval processes for new internally developed agents.
  • Ensure cross division reuse of agents.
  • Transform Analog and Digital Design
  • Define AI-enabled methodologies across:
  • Circuit design
  • Architecture exploration
  • RTL development
  • Verification
  • Physical design
  • Device characterization
  • Design reviews
  • Failure analysis
  • Documentation generation
  • Drive deployment of AI workflows into production engineering environments.
  • Identify high-value use cases capable of delivering significant improvements in development cycle time, engineering efficiency, and design quality.
  • Create the AI Governance Operating Model
  • Define AI governance policies for engineering workflows.
  • Establish standards for:
  • Model selection
  • Training data usage
  • Intellectual property protection
  • Security and access controls
  • Human-in-the-loop decision processes
  • Validation requirements
  • Auditability and traceability
  • Ensure responsible deployment of AI systems across engineering organizations.
  • Drive Measurable Business Outcomes
  • Establish KPI frameworks measuring:
  • NPD cycle time
  • Design productivity
  • Engineering efficiency
  • Agent reuse rates
  • AI adoption
  • Design quality improvements
  • Verification coverage improvements
  • IP creation velocity
  • Deliver measurable improvements in development throughput and engineering effectiveness.
  • Lead creation of an enterprise Agentic AI framework supporting: Analog design agents Digital design agents Verification agents Layout agents Test engineering agents Applications engineering agents Documentation and requirements agents Program management agents
  • Define AI-enabled methodologies across: Circuit design Architecture exploration RTL development Verification Physical design Device characterization Design reviews Failure analysis Documentation generation
  • Establish standards for: Model selection Training data usage Intellectual property protection Security and access controls Human-in-the-loop decision processes Validation requirements Auditability and traceability
  • Establish KPI frameworks measuring: NPD cycle time Design productivity Engineering efficiency Agent reuse rates AI adoption Design quality improvements Verification coverage improvements IP creation velocity

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