Senior Digital Design Engineer

Senior or Staff Digital Design Engineer

About Us

About the Role

Key Responsibilities

• Digital Design & RTL Development
• Develop microarchitecture for assigned digital blocks and subsystems
• Design, code, and maintain high-quality, synthesizable RTL
• Evaluate design tradeoffs involving performance, power, area (PPA), and testability
• Participate in design reviews and incorporate feedback into RTL implementation
• Integration & Implementation
• Integrate RTL into larger subsystem and SoC environments
• Support lint, CDC/RDC, synthesis, and design quality checks
• Collaborate with physical design teams to resolve implementation issues
• Assist with timing constraint development and timing closure activities
• Support logic equivalence checking (LEC) and implementation debugging
• Participate in functional and timing ECO development when required
• Design Quality
• Ensure designs meet functional, timing, power, and DFT requirements
• Support silicon bring-up, validation, and post-silicon debug activities
• Analyze and resolve design issues throughout the development lifecycle
• Cross-Functional Collaboration
• Work closely with verification, DFT, physical implementation, firmware, and systems teams
• Partner with architects and senior technical leaders to refine design requirements
• Contribute to continuous improvement of design methodologies and development processes
• Mentor junior engineers and share technical knowledge within the team (Staff level)

Qualifications

• This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
• 6+ years of digital IC design experience
• Strong hands-on RTL development experience using Verilog or SystemVerilog
• Experience designing digital blocks for complex SoCs or ASICs
• Solid understanding of: RTL design and microarchitecture SoC integration and standard on-chip interfaces Clocking, resets, CDC/RDC methodologies Synthesis and physical implementation considerations Timing constraints (SDC) and timing closure
• RTL design and microarchitecture
• SoC integration and standard on-chip interfaces
• Clocking, resets, CDC/RDC methodologies
• Synthesis and physical implementation considerations
• Timing constraints (SDC) and timing closure
• Experience with industry-standard EDA tools (Synopsys and/or Cadence)
• Strong debugging, analytical, and problem-solving skills
• Excellent communication and collaboration skills

Preferred

Compensation & Benefits

• Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000
• Stock option grant
• Comprehensive benefits package including health, dental, vision, and 401(k)