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Senior DFT Design/Micro Architect Engineer, Google Cloud

Google
Bengaluru, IND
Senior · 8+ years experience
Onsite
Discovered 2 weeks ago

Full Job Posting

Responsibilities

  • Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
  • Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
  • Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
  • 8 years of experience in the implementation and validation of DFT technologies.
  • Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
  • Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
  • Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field.
  • Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
  • Experience in fault modeling.
  • Experience in SoC cycles, silicon bringup, and silicon debug activities.

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