Senior DFT Design Engineer, Google Cloud

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high speed iOS, Analog DFT).
• Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
• Insert DFT logic, boundary scan, scan chains, DFT compression, logic BIST, TAP controller, clock control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.
• - Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high speed iOS, Analog DFT). - Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. - Insert DFT logic, boundary scan, scan chains, DFT compression, logic BIST, TAP controller, clock control block, and other DFT IP blocks. - Document DFT architecture, test sequences, and boot-up sequences associated with test pins. - Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.

Minimum qualifications:

Preferred qualifications:

Qualifications

• Minimum qualifications: - Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience. - 8 years of experience in the implementation and validation of DFT technologies. - Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion. - Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field. - Experience in fault modeling. - Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for multi die SoCs). - Experience in SoC cycles, silicon bringup, and silicon debug activities.