Senior Design Lead (US)

Job Summary

Key Responsibilities

• Own RTL integration at subsystem level, including integration of multiple IPs/functional blocks. Implement and validate IP-to-IP and subsystem connectivity, including clock, reset, control, and data interfaces. Work on Majellum-related integration and associated subsystem connectivity. Perform and drive closure of: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) RTL lint and structural/quality checks Connectivity checks Debug and resolve integration issues across multiple IP blocks. Define and maintain clean RTL hierarchy and subsystem partitioning. Work closely with Physical Design (PD) teams on hierarchy, partitioning, implementation constraints, and integration requirements. Collaborate with RTL design, DV, DFT, architecture, and PD teams through subsystem integration and signoff. Support design reviews, integration quality, issue tracking, and RTL readiness for downstream implementation. CDC/RDC, connectivity/static checks, debugging across IPs, and collaboration with physical design are also reflected in current SoC RTL integration roles.
• Own RTL integration at subsystem level, including integration of multiple IPs/functional blocks.
• Implement and validate IP-to-IP and subsystem connectivity, including clock, reset, control, and data interfaces.
• Work on Majellum-related integration and associated subsystem connectivity.
• Perform and drive closure of:
• CDC (Clock Domain Crossing)
• RDC (Reset Domain Crossing)
• RTL lint and structural/quality checks
• Connectivity checks
• Debug and resolve integration issues across multiple IP blocks.
• Define and maintain clean RTL hierarchy and subsystem partitioning.
• Work closely with Physical Design (PD) teams on hierarchy, partitioning, implementation constraints, and integration requirements.
• Collaborate with RTL design, DV, DFT, architecture, and PD teams through subsystem integration and signoff.
• Support design reviews, integration quality, issue tracking, and RTL readiness for downstream implementation.
• CDC/RDC, connectivity/static checks, debugging across IPs, and collaboration with physical design are also reflected in current SoC RTL integration roles.
• Strong experience in ASIC/SoC RTL design and subsystem integration.
• Strong hands-on knowledge of Verilog/SystemVerilog.
• Experience integrating multiple IPs/subsystems into complex SoC designs.
• Strong understanding of connectivity, clocks, resets, CDC and RDC.
• Experience with Lint and RTL quality/signoff methodologies.
• Good understanding of RTL hierarchy and design partitioning.
• Experience working with Physical Design teams and understanding PD-driven hierarchy/partition requirements.
• Strong debugging and problem-solving skills.
• Ability to work across RTL, DV, DFT and PD teams.
• SystemVerilog, IP integration, CDC, lint closure, and cross-functional work with verification, PD, and DFT are typical requirements in RTL integration positions.
• Experience with Majellum or similar subsystem/integration environments.
• Experience with large, multi-clock/multi-reset SoCs.
• Familiarity with synthesis, timing, low-power/UPF, DFT, and implementation flows.
• Scripting knowledge in Tcl, Python, Perl, or Shell.
• Experience taking a subsystem from RTL integration through quality/signoff and PD handoff.

Skill Requirements

Other Requirements

Qualifications

• Experience with Lint and RTL quality/signoff methodologies.
• Experience with Majellum or similar subsystem/integration environments.
• Experience with large, multi-clock/multi-reset SoCs.
• Familiarity with synthesis, timing, low-power/UPF, DFT, and implementation flows.