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Senior ASIC Physical Design Engineer

Google
Sunnyvale, USA
Senior · 7+ years experience
Onsite
USD 163000-236000 / year
Discovered 1 weeks ago
perlpython

Full Job Posting

Responsibilities

  • Participate in the physical design of complex blocks.
  • Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
  • Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 7 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
  • Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

  • Experience working with external partners on physical design (PD) closure.
  • Experience in static timing analysis (STA), with an understanding of how to define timing corners, margins and derates.
  • Experience with Synopsys/Cadence PnR tools.
  • Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
  • Understanding of DFT including Scan, MBIST and LBIST.
  • Understanding of performance, power and area (PPA) trade-offs.

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