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Senior ASIC Design Verification Engineer, Cloud

Google
Sunnyvale, USA
Senior · 10+ years experience
Onsite
USD 163000-236000 / year
Discovered 1 weeks ago

Full Job Posting

Responsibilities

  • Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience with design verification.
  • Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 10 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
  • Experience with the full verification life cycle.
  • Experience with three or more SoC projects/cycles and verifying interconnect IPs.

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