Senior ASIC Design Engineer - DSP/Analog/SerDes
Key Skills for This Role
Full Job Posting
Required Qualifications
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
- 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
- Strong proficiency in Verilog and/or SystemVerilog.
- Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
- Hands-on experience with ASIC design flows and industry-standard EDA tools.
- Strong knowledge of one or more of the following areas:
- Digital Signal Processing (DSP)
- High-speed SerDes
- Analog/Mixed-Signal ICs
- Digital communications
- Optical communications
- Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.
- Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.
- Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.
- Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
- Familiarity with verification methodologies such as UVM and/or formal verification.
- Knowledge of low-power design techniques and PPA optimization.
- Strong analytical and problem-solving skills.
- Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.
Preferred Qualifications
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
- Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
- Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
- Experience working with advanced semiconductor process technologies.
- Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
- Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
- Understanding of optical communication standards and high-speed networking protocols.
- Experience working in a startup or fast-paced semiconductor development environment.
- Why Join Celero?
- At Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.
- Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
About Celero Communications, Inc.
Celero Communications is a private semiconductor startup developing coherent DSPs for AI data-center optical connectivity.
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