Senior ASIC Design Engineer - DFT

We are now looking for a Senior ASIC Design Engineer to join our DFT team!

NVIDIA has continuously reinvented itself over two decades.

Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.

More recently, GPU deep learning ignited modern AI — the next era of computing.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world.

This is our life’s work, to amplify human imagination and intelligence.

Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.

You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.

Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs

Develop, deploy, and enhance DFT methodologies for scalability and future product needs

Define and align feature sets by working closely with architects, platform, and software teams

Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration

Create and execute test plans to support both functional and DFT full-chip verification

Support post-silicon bring-up and validation efforts including debug and issue resolution

Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance

What we need to see:

BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience

8+ years of hands-on experience in SoC architecture, RTL design, and verification

Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus)

in DFT design, methodology, and implementation

Familiarity with related domains such as clocking, STA, place & route, and power optimization

Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis

Proficiency in scripting languages such as Python, Perl, or Tcl

Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges

Ways to Stand out from the Crowd:

Experience with UVM-based verification environments

Experience designing fuse, eFuse, or on-chip security blocks

Proven track record of successfully architecting DFT IPs across multiple product generations

Why Join Us?

This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs.

At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world.

You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork.

We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

#LI-Hybrid

You will also be eligible for equity and benefits.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.