Semiconductor Product Engineer

Key Responsibilities

• Develop and maintain ATE test programs for an AI accelerator chip targeting high-volume manufacturing.
• Implement manufacturing test content for advanced CMOS designs including high-speed logic, SRAM, DRAM, and high speed IO blocks.
• Develop and debug structural and functional test content such as scan/ATPG, LBIST, MBIST, JTAG, and HSIO tests.
• Bring up first silicon on ATE, including pattern debug, tester correlation, shmooing, and corner analysis.
• Support testing of high-speed interfaces such as PCIe Gen6 and multi-GHz LPDDR, including at-speed tests and margining features.
• Execute silicon characterization and failure analysis to identify yield limiters and defect mechanisms.
• Optimize test coverage, test time, and cost while maintaining manufacturing robustness.
• Work with DFT and design teams to improve testability and close coverage gaps.
• Collaborate with OSATs and external partners on test program execution and debug under guidance from the test lead.
• Support advanced packaging test flows, including die-to-die interconnect testing and package-level thermal considerations.
• Contribute to documentation of test programs, debug procedures, and manufacturing release materials.
• Support qualification, reliability testing, and high-volume manufacturing ramp.

Required Qualifications

• 5+ years of hands-on semiconductor test engineering experience.
• Strong experience developing ATE test programs (Advantest 93K, Teradyne, or equivalent).
• Solid understanding of DFT methodologies (scan, ATPG, MBIST, LBIST) and memory test techniques.
• Experience debugging silicon issues at the tester and correlating failures to design or process causes.
• Familiarity with advanced CMOS nodes and production test challenges.
• Ability to work effectively in a cross-functional engineering environment.

Preferred Qualifications

• Experience testing AI accelerators, GPUs, networking ASICs, or other high-performance compute ICs.
• Experience with PCIe Gen5/Gen6, LPDDR4/5/6, or other high-speed interfaces.
• Exposure to advanced packaging, chiplets, or multi-die test flows.
• Experience improving yield, reducing test time, or optimizing cost in high-volume manufacturing.

How we work

About us

Export control and security clearance