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RTL Design Engineer, Silicon

Google
California, USA
Mid · 4+ years experience
Onsite
USD 138000-197000 / year
Discovered 2 weeks ago
perlpython

Full Job Posting

Responsibilities

  • Define microarchitecture for a subsystem.
  • Integrate internal or external IP.
  • Define microarchitecture of a small to medium size IP.
  • Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with IP development or integration.
  • Experience in ASIC development with Verilog or VHDL.
  • Experience with a scripting language like Perl or Python.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
  • Knowledge of high-performance and energy efficient design techniques.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of ASIC Verification or DFT.

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