RFIC - PLL Design Engineer
Key Skills for This Role
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Description
As a RFIC-PLL Designer, you are going to contribute to providing analog and digital PLL solutions for wireless SoC and driving them to mass production for Apple’s Wireless Connectivity products.
Minimum Qualifications
- BS and 10 + years of relevant industry experience.
- Experienced in design and development of Analog and Digital PLLs and LOGEN for high performance applications.
- Hands on experience in designing PLL building blocks: TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs and PFD/CP.
- Deep understanding of analog, mixed-signal and RF circuit design concepts. This includes LNAs, PAs, mixers, baseband filters, VGAs and calibration methods associated with high performance wireless systems.
- Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.
- Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS).
- Extensive experience in PLL and LOGEN silicon characterization and debug.
Preferred Qualifications
- Ph.D. degree
- Hands on experience in modeling, analysis and design of noise/spur cancellation techniques in PLLs.
- Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.
- Familiarity with timing analysis tools (Nanotime, Primetime).
- Direct experience in designing and bringing into mass production of wireless transceivers in deep sub-micron RFCMOS technology.
- Demonstrated capability to work with digital design group for an optimum partition between digital and analog and contribute to providing comprehensive timing requirements.
About Apple
Designing and manufacturing consumer electronics, software, and digital services.
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