Principal Engineer, Design Verification Engineering

About Analog Devices

About the Role

Responsibilities

• Lead end-to-end SoC verification for complex digital SoCs from planning through signoff.
• Verify microprocessor-based designs, AI/ML accelerators, and high-speed peripherals.
• Plan execution, track progress, and provide technical leadership, mentoring, and guidance.
• Collaborate with architecture and design teams on requirements and verification deliverables.
• Coordinate with emulation, FPGA, software, firmware, and system teams for pre-silicon and full-system validation.
• Develop system-level use cases and scalable UVM-based testbenches and verification flows.
• Drive test planning, functional and code coverage closure, formal verification, NoC verification, and performance analysis.
• Define verification strategy using formal verification, emulation, portable stimulus, and virtual platforms.

Requirements

• B.Tech or M.Tech with 12+ years of digital pre-silicon verification experience and leadership across IP, subsystem, or SoC-level verification.
• Hands-on expertise in Verilog/SystemVerilog, UVM testbench development, debugging, and methodology implementation.
• Experience with verification closure, NoC, buses, interconnects, power-aware verification using UPF, formal verification, and gate-level simulation.
• Protocol verification experience with interfaces including I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Experience in security and safety verification, test planning, constrained-random verification, assertions, and transaction-level modeling.
• Understanding of ARM, RISC-V, or Tensilica processor systems, AI/ML accelerators, C/C++, SystemC, and Python, TCL, or Shell scripting.
• Exposure to mixed-signal or analog verification is a plus.
• Excellent communication, leadership, collaboration, and problem-solving skills are required.

Schedule and Travel

• The position requires travel approximately 10% of the time.
• The shift is first shift during days.