Principal Design Verification Engineer

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification, with demonstrated technical ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM (Universal Verification Methodology), including development and optimization of UVM-based verification environments.
• Experience defining verification strategies and developing verification plans from design and product specifications.
• Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure.
• Experience partnering closely with RTL/design engineering teams throughout the verification lifecycle.
• Demonstrated ability to independently solve complex verification and design problems.
• Ability to provide technical leadership and mentoring within a verification team.
• Experience with DDR, memory interfaces, memory controllers, data buffers, or related semiconductor technologies.
• Experience with DDR4 and/or DDR5.
• Verification experience with complex high-speed interfaces, protocols, or mixed-signal semiconductor products.
• Experience leading verification efforts through coverage closure and signoff.