Principal ASIC Design Engineer

Responsibilities:

• Architect complex modules and subsystems used in high performance networking chips.
• Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.
• Implement the design using Verilog or System Verilog
• Write functional coverage/SVA to help verification catch corner case bugs.
• Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
• Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.
• Collaborate with the Verification team to make sure your block is fully validated.
• Show leadership and provide guidance to new college-grad/junior engineers and interns.
• Recommended skills
• Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 15+ years of relevant experience.
• Strong analytical/ problem solving skills.
• Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.
• Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
• Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
• Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.
• Excellent written and verbal communications skills is necessary.
• Knowledge of Perl/Python is strongly desired.
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