Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Preferred Qualifications

• Worked in DV methodology and definition of high-scale, high-performance ASICs.
• Planning overall DV architecture strategy and defining the requirements.
• Conducting & leading various test plan reviews.
• Driving complex debugs and system level integration aspects
• Valid experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
• Mentoring the senior resources in the team on DV and DV methodologies.
• Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
• Excellent communication skills both verbal and written

Why Cisco?

Qualifications

• BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.
• Have led a design team for a minimum of 5+ years
• Must have prior experience of developing UVM based infrastructure from scratch in more than one projects.
• Ability to handle complex features/parts of chip independently.
• Quick learner must be able to work in a fast pace dynamic environment and must be able to deliver quality even in aggressive schedule.
• Strong teamwork quality – must be able to work in a highly collaborative team.
• Overseeing reusability, comes up reusable solution to improve efficiency. Must always focus on efficiency and quality.
• Ability to build, lead and mentor a team of engineers and ensuring quality delivery as a team.
• Proficient in merging and analyzing code coverage data generated functional simulation
• Good working knowledge in C, C++ programming and debugging skills
• Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.
• Hardware Emulation Platforms and tools (such as EVE, Veloce)
• Good written/verbal interpersonal skills and leadership skills.
• Worked in DV methodology and definition of high-scale, high-performance ASICs.
• Planning overall DV architecture strategy and defining the requirements.
• Conducting & leading various test plan reviews.
• Driving complex debugs and system level integration aspects
• Valid experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
• Mentoring the senior resources in the team on DV and DV methodologies.
• Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
• Excellent communication skills both verbal and written
• Why Cisco?
• At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
• Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
• We are Cisco, and our power starts with you.
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