Lead IP Verification Engineer

The Role

Key Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand features to be verified.
• Develop test plan documentation covering interactions with features, hardware, firmware, and software-driver use cases.
• Code IP- or subsystem-level UVM testbenches and verification components, including monitors, scoreboards, and checkers.
• Build directed and random verification tests.
• Run regressions and debug test failures to ensure functional, performance, and implementation quality.

Preferred Experience

• Proficiency in IP-level ASIC verification.
• Expertise in Verilog, SystemVerilog, and object-oriented programming.
• Expertise developing UVM-based verification frameworks and testbenches.
• Scripting and automation of verification processes and flows.
• Exposure to simulation profiling, efficiency improvement, acceleration, and HLS tools or processes.
• Computer architecture and systems knowledge.
• Comfort with Python or Perl and maintaining scripts.
• Leadership or mentorship exposure is an asset.
• Experience across the ASIC project lifecycle from planning to tape-out.
• Experience with PCIe, CXL, NVMe, or Ethernet protocols.
• Strong communication skills and ability to work independently and in a cross-site team environment.

Academic Credentials

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.

Benefits

• Benefits are described in AMD’s benefits overview.