Lead Full-chip STA and timing signoff Engineer

Role overview

Key responsibilities

• Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners.
• Own timing signoff from synthesis through final tapeout.
• Develop, validate, and maintain full-chip and block-level SDC constraints.
• Perform and review STA for setup, hold, recovery, removal, clock gating, and asynchronous paths.
• Drive MMMC methodology and timing convergence across PVT corners.
• Collaborate on floorplanning, placement, CTS, routing, and post-route timing optimization.
• Resolve violations involving datapath, clock path, crosstalk, noise, OCV/AOCV/POCV, derates, and variation.
• Lead timing ECO closure while minimizing impact to power, area, and performance.
• Coordinate timing budgets, interface closure, and hierarchical signoff with IP and block owners.
• Lead tapeout readiness reviews, provide timing-risk assessments, mentor junior engineers, and define best practices.

Preferred experience

• Bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or Computer Engineering.
• 12+ years of hands-on ASIC/SoC timing analysis and timing closure experience.
• Strong full-chip STA and timing signoff experience for large-scale SoCs.
• Experience with advanced technology nodes such as 7nm, 5nm, 3nm, or similar.
• Knowledge of synthesis, place-and-route, extraction, and signoff flows.
• Experience with timing budgeting and hierarchical/full-chip integration.
• Understanding of clocking architecture, CDC implications, and timing exception handling.
• Ability to debug complex timing issues and drive closure under aggressive schedules.
• Strong communication, stakeholder management, and leadership skills.

Additional information