Lead DFT Engineer

B.Tech / M.Tech in Electronics, Electrical, or related field

5–8 years of experience in core DFT

Strong expertise in ATPG and LBIST methodologies

Solid hands-on experience in scan insertion and compression

Strong understanding and hands-on experience with iJTAG (IEEE 1687)

Experience in MBIST architectures and repair flows

Good understanding of Boundary Scan / JTAG and related standards (1149.1, 1500, 1687 preferred)

Exposure to low-power DFT concepts

Experience in testability analysis and silicon debug

Strong problem-solving and debugging skills

Ability to work in a cross-functional team environment

Good communication and mentoring skills

Lead end-to-end DFT implementation for SoC subsystems

Drive DFT RTL integration and verification activities

Manage cross-functional coordination for DFT deliverables at block/subsystem level

Implement full-scan DFT methodologies

Develop and optimize scan insertion and compression techniques

Execute ATPG flows to achieve required fault coverage

Define and implement MBIST architectures, including repair flows

Support LBIST planning and implementation

Implement and ensure compliance with Boundary Scan / JTAG requirements

Apply low-power DFT methodologies

Perform testability analysis and improve design coverage

Support silicon debug and failure analysis

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