Layout Engineer, Power Modules

Key Responsibilities

• Design and edit power-module and silicon-interposer layouts, including die placement, power and signal routing, pads, and top-level assembly, using the relevant PDK and IP views.
• Own assigned module layouts from floorplan through implementation, and keep layout decisions traceable across variants and revisions.
• Run and interpret DRC, LVS, and parasitic extraction, and use the results to correct layout before it moves downstream.
• Prepare layouts for design release: stream-out, database transfer, and the evidence expected at tapeout.
• Use KLayout for layout review and scripted edits, and help extend the same workflow to Cadence Virtuoso and the other tools used for power-module development.
• Identify the tool actions an AI agent needs in order to create, edit, inspect, and check a layout, including required inputs, safe bounds, and expected outputs.
• Validate AI-produced layouts against the source design, PDK rules, connectivity, and known-good results. Reject output that is geometrically valid but electrically or physically wrong.
• Contribute layout requirements to platform feature discussions, including candidate review, violation markup, net tracing, and revision comparison.
• Capture layout practices, layer and design-rule knowledge, and tapeout checks that currently depend on individual designers, so they can be reused by engineers and AI agents.
• Work with simulation, model-generation, and software engineers so layout, extraction, and model inputs stay consistent through the design flow.
• # LI-VS1

Required Skills

• 4 to 8 years of hands-on IC or power-module layout, including released or tapeout-ready work.
• Strong Cadence Virtuoso Layout experience, including Layout XL, schematic-driven layout, and PDK or PCell-based design.
• Practical use of Siemens Calibre for DRC and LVS, and working knowledge of PEX or another parasitic-extraction flow.
• Understanding of how floorplan, placement, routing, pads, and top-level assembly affect resistance, loop inductance, current density, and thermal behavior in a power module.
• Experience taking a layout through stream-out and database transfer, with familiarity with Cliosoft SOS or an equivalent design-data system.
• Ability to inspect GDS or OASIS and make controlled edits with KLayout, Calibre DESIGNrev, or equivalent layout tooling.
• Enough Python or SKILL to automate repetitive layout, query, or checking tasks, and to explain a manual tool action clearly enough for a software engineer to implement it.
• Careful review of generated layout against design intent, design rules, and connectivity, including the judgment to reject a result that only looks correct.
• Clear communication with layout, simulation, CAD, and software engineers, and comfort working from Linux design environments.

Preferred Skills

• Layout experience with SiC or other wide-bandgap multi-die power modules, silicon interposers, or heterogeneous integration.
• Familiarity with the onsemi power-module flow across die, interposer, package, and system, including Ansys Q3D, R3D, and thermal or mechanical checks driven by layout.
• Experience with Virtuoso SKILL, Python layout APIs, or batch verification flows.
• Exposure to pads and ESD, bonding-diagram generation, reticle or database release, and fab or process feedback.
• Interest in AI-assisted layout, AI agent tool use, or reviewing AI-generated engineering output. Prior AI product experience is not required.
• Experience contributing design-rule, PDK, or layout-review knowledge to an internal platform or automation project.
• # LI-VS1

About Company

Company

More details about our company benefits can be found here

• https://www.onsemi.com/careers/career-benefits

Requirements

• 4 to 8 years of hands-on IC or power-module layout, including released or tapeout-ready work.
• Strong Cadence Virtuoso Layout experience, including Layout XL, schematic-driven layout, and PDK or PCell-based design.
• Practical use of Siemens Calibre for DRC and LVS, and working knowledge of PEX or another parasitic-extraction flow.
• Understanding of how floorplan, placement, routing, pads, and top-level assembly affect resistance, loop inductance, current density, and thermal behavior in a power module.
• Experience taking a layout through stream-out and database transfer, with familiarity with Cliosoft SOS or an equivalent design-data system.
• Ability to inspect GDS or OASIS and make controlled edits with KLayout, Calibre DESIGNrev, or equivalent layout tooling.
• Enough Python or SKILL to automate repetitive layout, query, or checking tasks, and to explain a manual tool action clearly enough for a software engineer to implement it.
• Careful review of generated layout against design intent, design rules, and connectivity, including the judgment to reject a result that only looks correct.
• Clear communication with layout, simulation, CAD, and software engineers, and comfort working from Linux design environments.
• Layout experience with SiC or other wide-bandgap multi-die power modules, silicon interposers, or heterogeneous integration.
• Familiarity with the onsemi power-module flow across die, interposer, package, and system, including Ansys Q3D, R3D, and thermal or mechanical checks driven by layout.
• Experience with Virtuoso SKILL, Python layout APIs, or batch verification flows.
• Exposure to pads and ESD, bonding-diagram generation, reticle or database release, and fab or process feedback.
• Interest in AI-assisted layout, AI agent tool use, or reviewing AI-generated engineering output. Prior AI product experience is not required.
• Experience contributing design-rule, PDK, or layout-review knowledge to an internal platform or automation project.
• # LI-VS1