IC Layout Designer

Job Title

Job description

Responsibilities

• Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.
• Work from circuit schematics to create clean, compact, and manufacturable layouts.
• Perform layout of devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.
• Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.
• Run and debug physical verification checks including DRC, LVS, ERC, antenna checks, density checks, and reliability checks .
• Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.
• Support layout floorplanning, block-level integration, and top-level chip assembly.
• Follow foundry design rules and process-specific layout guidelines.
• Work with design engineers to optimize layout for performance, area, power, yield, and reliability.
• Prepare layout databases for tapeout and support final verification signoff.

Required Qualifications

• Associate degree, bachelor’s degree, or equivalent experience in electrical engineering, microelectronics, or a related field.
• Experience with IC layout tools such as Cadence Virtuoso Layout Suite .
• Good understanding of CMOS device layout and semiconductor process layers.
• Experience running and debugging DRC/LVS using tools such as Calibre, Assura, Pegasus, or similar.
• Ability to read and understand circuit schematics.
• Strong attention to detail and ability to follow layout guidelines.
• Understanding of parasitic effects, device matching, shielding, and signal integrity.
• Good communication skills and ability to work closely with circuit designers.

Preferred Qualifications

• Experience with analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I/O.
• Experience with advanced CMOS nodes such as 28 nm, 16 nm, 12 nm, 7 nm, or similar.
• Knowledge of FinFET layout rules and advanced-node restrictions.
• Experience with top-level integration, power routing, ESD planning, and chip finishing.
• Familiarity with electromigration, IR drop, latch-up prevention, and reliability rules.
• Experience with layout automation, SKILL scripting, or Python is a plus.

Key Skills

• Cadence Virtuoso
• DRC / LVS / ERC
• Calibre / Pegasus / Assura
• Analog layout
• Mixed-signal layout
• CMOS layout
• Device matching
• Parasitic extraction
• Shielding and isolation
• Floorplanning
• Top-level integration
• Tapeout support