Hardware Design Engineer, High Speed Networking

Authoring functional specifications of high power and high density Ethernet switches used in AI networks

Selecting and qualifying components

Schematic capture and tool-based design verification

Working closely with eCAD teams on PCB layout and component footprints

Working with internal teams to run (or run your own) signal integrity simulations on both power and datapath signals

Working closely with mechanical and thermal engineers on the system general arrangement and physical realization

Specifying PCB stackup and fabrication details with various PCB vendors

Working with internal teams to develop (or develop your own) programmable logic devices for control and timing planes

Working closely with local and overseas Contract Manufacturers (CM), from proto through production

Lab bring up and debug of prototypes

Working closely with diagnostics software engineers on both design validation and manufacturing test development

Driving complex system debug between software, hardware, and test teams

Training CM for high yield test and manufacturing

BSEE or MSEE

2+ years of relevant experience in hardware engineering (extremely promising new graduates will also be considered).

Solid understanding of basic electronics theory and design

Experience with circuit design and debug, especially involving high speed signals

Experience with lab debug and test equipment

Experience learning complex design tools

Familiarity with signal integrity and power integrity concepts

FPGA design and system simulation experience is a plus

Some Python or other coding experience is a plus

#LI-FI1

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.