Formal Verification Engineer

THE ROLE

REQUIREMENTS — MUST HAVE

• Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, with hands-on formal verification.
• Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence.
• Strong Verilog/SystemVerilog and assertions / temporal logic.
• Strong knowledge of CPU micro-architecture and digital logic.
• Strong scripting (Python; TCL/Perl a plus), analytical, and debug skills.

REQUIREMENTS — NICE TO HAVE

• Proficiency with industry formal tools (e.g. Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).
• Taking complex verification problems to proof closure — abstraction, bounded-proof management, and equivalence checking (LEC/SEC) against golden references.
• Formal verification of CPU domains such as cache coherence, memory consistency, speculative execution, or data path.
• Security formal verification or theorem proving.
• Understanding of how formal complements dynamic simulation, and shared assertion libraries.
• Mentoring engineers and collaborating across distributed teams.
• Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Formal Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the Nuvacore CPU correct with formal methods. As part of the design verification (DV) team , you will turn micro-architecture specifications into properties, build the environments to prove them, and use model checking and equivalence checking to exhaustively hunt deep, corner-case bugs — establishing correctness long before silicon, working shoulder-to-shoulder with the design team.