Digital Verification Engineer

What You'll Do

Required Qualifications & Experience

Ways to Stand Out

Qualifications

• 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout.
• UVM and SystemVerilog: Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests.
• Coverage: Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
• Assertions: Working knowledge of SystemVerilog Assertions.
• Debug Skills: Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
• Scripting & Automation: Proficiency in Python for test automation, log analysis, and regression flows.
• Communication: Ability to clearly report verification status and issues to the team.
• Ways to Stand Out
• C/C++ experience for reference models or DPI-based verification.
• Exposure to formal verification (JasperGold or similar).
• Experience building or using AI agentic flows for DV.
• Knowledge of computer architecture or dataflow architectures.
• Exposure to power-aware verification (UPF)
• Why Join Efficient?
• Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

Preferred Qualifications

• We offer a competitive base salary for this role, generally ranging from $130,000 to $180,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.
• Debug simulation failures, working with designers to root-cause and fix issues.
• Contribute to regression infrastructure, automation, and dashboards that track verification progress.
• Support gate-level simulation and other sign-off activities.
• Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout.
• UVM and SystemVerilog: Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests.
• Coverage: Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
• Assertions: Working knowledge of SystemVerilog Assertions.
• Debug Skills: Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
• Scripting & Automation: Proficiency in Python for test automation, log analysis, and regression flows.
• Communication: Ability to clearly report verification status and issues to the team.
• C/C++ experience for reference models or DPI-based verification.
• Exposure to formal verification (JasperGold or similar).
• Experience building or using AI agentic flows for DV.
• Knowledge of computer architecture or dataflow architectures.
• Exposure to power-aware verification (UPF)
• We offer a competitive base salary for this role, generally ranging from $130,000 to $180,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
• Why Join Efficient?
• Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.