DFT Timing Lead

Role Overview

Key Responsibilities

• Develop full-chip DFT synthesis and DFT STA constraints.
• Develop STA constraints for ScanShift, ATspeed, and MBIST DFT modes.
• Set up DFT timing constraints and define the SoC test STA methodology.
• Work with design teams to resolve DFT-related constraint issues.
• Work with physical design teams to generate and validate timing constraints.
• Develop, improve, and maintain automation scripts.

Preferred Experience and Qualifications

• Experience in DFT architecture for complex chips is preferred.
• Exposure to static timing analysis and timing closure is required.
• Experience handling DFT constraints and block- and top-level test-mode STA is preferred.
• Experience in SoC timing closure in DFT modes and sign-off is preferred.
• Experience with Spyglass, CDC, Lint, or similar RTL quality-check tools and methodologies is required.
• Excellent hands-on debugging and scripting skills are required.
• B.E., B.Tech, M.E., or M.Tech in Electrical or Electronics Engineering is required.
• The role requires 8–15 years of DFT experience.

Workplace

• The posting includes a hybrid workplace designation.