DFT Principal Engineer

Role and product group

Responsibilities

• Lead DFT work across scan implementation methods including stuck-at, MBIST, iJTAG, BSCAN, transition, and bridge faults.
• Provide timing constraints for scan modes and run pattern simulation with zero delay and SDF.
• Analyze coverage and suggest design improvements.
• Fix low-power issues after DFT implementation and perform post-silicon debug.
• Use Verilog and scripting languages; improve existing flows and methods to positively affect PPA.
• Apply strong problem-solving skills and deep technical understanding.

Qualifications

• BS in Electrical Engineering or a related field plus 12 years of experience, or MS plus 11 years of experience.
• Experience working on and leading digital design, architecture, and ASIC/mixed-signal chip development.
• Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis, P&R, and UPF.
• Solid understanding of Verilog, TCL, and Perl, Python, or XML programming languages.
• Track record of releasing complex ICs to market.
• Ability to articulate issues, challenges, and concerns to all levels of management; good written and verbal cross-functional communication skills.

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