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Design Verification Manager

Texas Instruments
IND
Manager · 8+ years experience
Discovered 1 months ago
perlpython

Full Job Posting

Responsibilities:

  • Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:
  • Build, Mentor and scale high preforming verification team across IP, Subsystem and SoC level
  • Lead verification activities for overall verification strategy, methodology, infrastructure and execution plans across multiple SoC programs.
  • Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics.
  • IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
  • DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs
  • Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities
  • Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines
  • Active involvement in the customer reviews and certifications (ISO26262/ISO21434).

Qualifications:

  • 8+ years of DV experience in IP/SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations
  • Qualifications: • 8+ years of DV experience in IP/SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Skills: - Strong people management skills along with experience in leading DV projects - First pass success silicon success enablement by working closely with team members as well as various cross functional teams - Experience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc. - Thorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet. - Work experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus. - Strong understanding of digital design fundamentals, computer organization and architectures, and bus protocols. - Excellent Analytical, debugging skills with Verilog/VHDL designs. - Good problem-solving skills. - Experience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows. - Proficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous. - Effective communication skills to interact seamlessly with all stakeholders. - Must be highly focused and committed to achieving project goals. - Ability to quickly ramp up on new systems and processes while maintaining the time management skills necessary for on-time delivery.

Skills:

  • Strong people management skills along with experience in leading DV projects
  • First pass success silicon success enablement by working closely with team members as well as various cross functional teams
  • Experience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc.
  • Thorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet.
  • Work experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus.
  • Strong understanding of digital design fundamentals, computer organization and architectures, and bus protocols.
  • Excellent Analytical, debugging skills with Verilog/VHDL designs.
  • Good problem-solving skills.
  • Experience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows.
  • Proficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous.
  • Effective communication skills to interact seamlessly with all stakeholders.
  • Must be highly focused and committed to achieving project goals.
  • Ability to quickly ramp up on new systems and processes while maintaining the time management skills necessary for on-time delivery.

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