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Design Verification Engineer

Texas Instruments
Bengaluru, IND
Junior · 1–3 years experience
Onsite
Discovered 2 days ago
perlpython

Full Job Posting

Qualifications

  • Core Qualifications
  • Education: Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
  • Mixed-Signal Fundamentals: Strong understanding of analog building blocks, digital design processes, and top-level integration.
  • Verification Expertise: Proven experience in developing mixed-signal testbenches in SV/UVM from scratch, including the ability to debug and optimize simulation performance and understand necessary trade-offs.
  • Debug Skills: Strong simulation debug capability with the ability to analyze waveforms and pinpoint issues in schematic simulations or models, including ability to read and interpret analog transistor level schematics and RTL codes.
  • Controller Knowledge: Familiarity with analog controllers to develop system-level testbenches and debug complex issues.
  • Soft Skills
  • Drive: A self-driven individual with a thirst for continuous learning.
  • Communication: Excellent interpersonal and communication skills.
  • Teamwork: A collaborative attitude with the ability to function effectively both independently and within a team.
  • Preferred Skills & Experience
  • Experience: 1–3 years of professional experience in mixed-signal design verification.
  • Tool Proficiency: Expertise in Cadence Mixed-Signal Design Environment tools (Virtuoso, ADE Assembler, Xcelium, VIVA, and Simvision).
  • Simulation Mastery: Expertise in Cadence Spectre simulation testbench development, regression flows, and debugging.
  • HDL Mastery: Advanced proficiency in SystemVerilog, UVM, and Verilog-AMS; experience writing checkers, assertions, and monitors for top-level simulations.
  • Automation: Proficiency in automation using Python, Perl, Tcl, or Shell scripting.
  • 1–3 years of professional experience in mixed-signal design verification.

Preferred Qualifications

  • Preferred Skills & Experience

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