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Design Verification Engineer - APS

Texas Instruments
Santa Clara, USA
Senior · 8+ years experience
Onsite
Discovered 1 weeks ago
python

Full Job Posting

Qualifications

  • Minimum requirements
  • Minimum education (i.e., bachelor's degree in electrical engineering)
  • Minimum of 8+ years of experience

Preferred qualifications:

  • Experience using UVM, Verilog, SystemVerilog, Python
  • Developing verification strategies, and building scalable UVM-based testbenches
  • Drive functional and code coverage to closure
  • Participate in code and testbench reviews, mentor junior team members, and contribute to methodology improvements
  • Strong background with EDA design tools and UNIX design environment
  • Understanding of analog circuits and systems, particularly power systems
  • Experience with formal verification methods and tools
  • Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
  • Strong verbal and written communication skills and an ability to work directly with customers
  • Ability to quickly ramp on new systems and processes
  • Demonstrated strong interpersonal, analytical and problem-solving skills
  • Ability to work in teams and collaborate effectively with people in different functions
  • Ability to take the initiative and drive for results
  • Strong time management skills that enable on-time project delivery
  • Strong verbal and written communication skills

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