Design Verification Engineer - Analog Mixed-Signal (AMS) | BCP

Qualifications

• Basic Requirements (Must-Haves)
• Education: Bachelor’s or master’s degree in electrical engineering (EE) or Electronics and Communication Engineering (ECE)
• Experience: Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification.
• Modelling Skills: Proficiency in analog behavioral modelling using System Verilog, Verilog-AMS, Verilog-A, or Wreal.
• Verification Flow: Direct experience with mixed-signal verification involving a combination of schematic, behavioral models, and RTL.
• Tool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed-signal simulation tools
• Communication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders.
• Excellent self-organizing and time management skills.
• Preferred Skills & "Good to Have" (Innovation & Automation)
• Advanced DV: Knowledge of UVM, as the top-level environments are built on these frameworks.
• Automation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis. Exposure and interest in building AI-driven verification methodologies.
• Domain Expertise: Experience in signal processing, PMICs, or high-speed communication interfaces.
• Silicon Interaction: Experience in silicon debug and working alongside silicon validation teams.
• Standard protocols exposure: Verification experience with I2C, SPI, UART etc.
• Basic Requirements (Must-Haves) - Education: Bachelor’s or master’s degree in electrical engineering (EE) or Electronics and Communication Engineering (ECE) - Experience: Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification. - Modelling Skills: Proficiency in analog behavioral modelling using System Verilog, Verilog-AMS, Verilog-A, or Wreal. - Verification Flow: Direct experience with mixed-signal verification involving a combination of schematic, behavioral models, and RTL. - Tool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed-signal simulation tools - Communication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders. - Excellent self-organizing and time management skills. Preferred Skills & "Good to Have" (Innovation & Automation) - Advanced DV: Knowledge of UVM, as the top-level environments are built on these frameworks. - Automation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis. Exposure and interest in building AI-driven verification methodologies. - Domain Expertise: Experience in signal processing, PMICs, or high-speed communication interfaces. - Silicon Interaction: Experience in silicon debug and working alongside silicon validation teams. - Standard protocols exposure: Verification experience with I2C, SPI, UART etc.