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Design Engineer II

Cadence Design Systems
Uttar Pradesh, IND
Full-time
Onsite
Discovered 3 weeks ago
SystemVerilogUVMC/C++RTLProcessor integrationRISC-V

Full Job Posting

Role overview

The role focuses on design verification infrastructure and processor verification.

Key responsibilities

  • Develop simulation testbenches in C/C++ and RTL and lead reusable UVM environment development.
  • Promote formal verification and AI-driven coverage analysis.
  • Coordinate with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required qualifications

  • B.Tech or M.Tech in ECE.
  • Experience with SystemVerilog/UVM and C/C++ for architectural modeling.
  • Processor integration experience, such as RISC-V or ARM, and protocols such as AMBA or PCIe.
  • Perl, Python, or Tcl scripting experience for verification automation.
  • Experience verifying complex pipelines, memory subsystems, or ISA implementations.

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