Custom SOC IP Verification Engineer

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NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions!

We are looking for special individuals with desire to deliver innovative products.

Together, we will build the next generation of life changing custom SOCs!

If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.

This role specifically requires a skilled ASIC Verification Engineer with expertise in fabric and interconnect verification, spanning both IP and SoC integration.

You will play a key role in verifying the correctness, performance, and compliance of on-chip fabrics and interconnect subsystems — from IP bring-up through full chip integration — ensuring robust and high-performance connectivity across complex SoC designs.

This position demands a motivated individual who understands how complex SOCs and IPs are built, has intimate knowledge of client requirements, and comprehends various development cycles.

It requires deep knowledge of SystemVerilog and UVM, along with a solid grasp of ASIC verification methodologies.

What you'll be doing:

Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.

Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.

Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.

Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.

Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

What we need to see:

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).

6+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full chip levels.

Strong knowledge of SystemVerilog and UVM methodology.

Hands-on experience with industry-standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), with solid understanding of ordering, coherency, and flow control semantics.

Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.

Proficiency in scripting languages (Python, Perl, TCL).

Ways to stand out from the crowd:

Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics.

Exposure to verification IPs for bus protocols, or emulation platforms (e.g., Palladium, Veloce) for full chip fabric validation.

in GPU or AI accelerator SoC interconnect verification is desirable.

with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package.

As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

You will also be eligible for equity and benefits.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.