CPU Performance Modeling (Lead & ICs)

Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.

Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).

Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.

Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.

Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.

Contribute to IP development through patents and, where applicable, external publication

Performance model: Cycle-accurate C++ simulator — architecture, calibration, and correlation against RTL and silicon.

Workload analysis: Benchmark characterization (SPEC, Geekbench, AI/ML, cloud, client traces) and bottleneck identification.

Microarch exploration: PPA trade-off studies and feature proposals across the full CPU pipeline — frontend through memory subsystem.

Cross-team alignment: Architecture-to-implementation bridge: design, verification, compiler, and OS/system software partners