CPU Fabric and Interconnect Verification Engineer

Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non-coherent, including crossbars, routing, and bus interfaces.

Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non-coherent transactions end to end.

Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.

Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.

Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.

Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.

15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.

Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport.

Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.

Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).

Experience writing and debugging tests for complex digital designs.

Interconnect, network-on-chip (NoC), or fabric verification.

Coherent and non-coherent bus-protocol verification.

Protocol checkers and formal verification (deadlock/livelock, protocol compliance).

Constrained-random verification and coverage-driven closure.

Performance and QoS verification of interconnect.

Emulation/FPGA and silicon bring-up and debug (waveforms, trace).