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Chip Package Signal and Power Integrity Engineer

Google
Sunnyvale, USA
Senior · 7+ years experience
Onsite
USD 163000-236000 / year
Discovered 1 weeks ago
matlabpython

Full Job Posting

Responsibilities

  • Lead SI/PI analysis for High-Performance Computing (HPC) utilizing 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists.
  • Drive next-generation memory interface development and evaluate high-speed Interface IPs, balancing complex trade-offs across IO PHY, SI/PI, and physical design.
  • Own post-silicon validation and qualification of high-speed interfaces to ensure successful New Product Introduction (NPI).
  • Partner with chip/system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs.
  • Provide crucial feedback on chip floorplans to maximize package/system routability and SI/PI, while developing methodologies to improve simulation accuracy and productivity.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 7 years of experience with SI/PI design for chip/package or system PCB.
  • Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering or SI/PI.
  • Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
  • Knowledge of next-generation memory and chiplet standards, including timing budget, design and sign-off methodologies.
  • Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
  • Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.
  • Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.

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